This application claims the priority benefit of Taiwan application serial no. 88102910, filed Feb. 26, 1999, the full disclosure of which is incorporated herein by reference.
1. Field of the Invention
This invention relates to computer technology, and more particularly, to a debugging device for use in a system controller chip on a computer motherboard, such as a Pentium-based computer motherboard, to allow an on-site debugging procedure on the system controller chip so as to correctly lead signals to the integrated circuit (IC) leads.
2. Description of Related Art
In this information age, the IBM-compatible (or called Pentium-based) personal computers (PC) have become an indispensable office tool in all works of life, which can run various applications as data processing, multimedia, network, electronic mailing, and so on. A PC is typically constructed on a motherboard which is mounted with various components such as a CPU (central processing unit) for processing data; a chipset containing a system controller for controlling the transfer of input/output data to and from the CPU; a primary memory unit, typically a DRAM (dynamic random-access memory) unit for storing computer data; and various expansion means, such as an AGP (Accelerated Graphic Port) interface for connection to a monitor and PCI (Peripheral Component Interconnect) buses for connection to various other peripheral devices.
FIG. 1 is a schematic block diagram showing the basic system configuration of a typical PC motherboard, which includes a system controller 100, a CPU 102, a memory unit 104, and a graphic adapter 106. These components are interconnected via buses 108. The system controller 100 is typically contained in a single chipset and is used to control the transfer of I/O data between the CPU 102, the memory unit 104, and the graphic adapter 106 via the buses 108.
Debugging is an important task that must be constantly performed on the system controller 100 to check for any failed circuit parts in the system controller 100. With today""s high-performance PCs, however, the system controller 100 is becoming more and more complex in its internal architectures, particularly in the FIFO (First-in First-out) buffers and pipelined architectures. When a malfunction occurs, such a high architectural complexity in the system controller 100 would make the debugging highly difficult to carry out. Moreover, when performing a debugging procedure, the external circuitry would be unable to monitor the debugging procedure in an on-site manner.
By the conventional architecture, when a malfunction occurs to the system controller 100, the debugging procedure would firstly involve the use of a chemical solution to etch away the top of the resin compound used to seal the chipset of the system controller 100, and secondly the use of a microscope to visually aid the forming of a plurality of test pads on the chip. These test pads are then used to connect the internal circuitry of the system controller 100 to a test unit that can perform a test on all function blocks in the system controller 100 to check where the malfunction occurs.
One drawback to the use of chemical solution to uncover the chip, however, is that it would easily cause erosion to the chip, thus damaging the internal circuit of the chip. Moreover, the use of microscope in the forming of test pads is quite laborious and inconvenient for the test engineer to carry out. Furthermore, since a system controller chip is typically included with a plurality of function blocks and only one of them can be selected for test at a time, the debugging procedure is often carried out in a trial-and-error manner, which is quite inefficient and requires highly-experienced test engineers to perform. Still moreover, if the debugging procedure is performed in test mode, the test equipment would be unable to simulate the noises that would occur during the operation of the system controller chip, which would make the results of the debugging quite unreliable.
It is therefore an objective of this invention to provide a debugging device for use in a PC system controller chip, which can be controlled by the BIOS of the PC to perform an on-site debugging procedure on the PC system controller chip whenever a malfunction occurs to the system controller chip.
It is another objective of this invention to provide a debugging device for use in a PC system controller chip, which allows an on-site debugging procedure on the system controller chip through the use of on-site test.
It is yet another objective of this invention to provide a debugging device for use in a PC system controller chip, which allows the system controller chip to undergo a benchmark test to test all the function blocks in the system controller chip.
In accordance with the foregoing and other objectives of this invention, a novel debugging device is provided for use in a PC system controller chip. The debugging device of the invention is provided for use in a system controller chip on a computer motherboard, such as a Pentium-based computer motherboard, to facilitate a debugging procedure on the system controller chip whenever a malfunction occurs to the system controller chip. Under normal operating conditions of the system controller chip, the debugging device connects the connecting-pad area to the control unit and disconnects the connecting-pad area from the function blocks. In the event of a malfunction to the system controller chip, the debugging device responsively disconnects the connecting-pad area from the control unit and connects the connecting-pad area successively in a predetermined sequence to the function blocks, allowing the function blocks to undergo an on-site debugging procedure one by one. The debugging device allows an on-site debugging procedure on the system controller chip in real time, and also allows the system controller chip to undergo a benchmark test to check for the reliability in the overall functionality of the system controller chip.